drivertools: Utility code for indexing and traversing signal drivers #4328
+2,620
−0
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
This is a work in progress version of a new yosys kernel utility to simplify netlist traversal. The motivating use case is the upcoming functional backend but it also should also simplify some common operations/queries that come up repeatedly in various passes.
It adds
DriveBit
,DriveChunk
andDriveSpec
types which are similar toSigBit
,SigChunk
andSigSpec
but can also directly represent cell ports, undriven bits and multiple drivers. For indexing an RTLIL module and for querying signal drivers it comes with aDriverMap
type which is somewhat similar to aSigMap
but is guaranteed to produce signal drivers as returned representatives.A
DriverMap
can also optionally preserve connections via intermediate wires (e.g. querying the driver of a cell input port will return a connected intermediate wire, querying the driver of that wire will return the cell output port that's driving the wire). Currently the behavior is hard-coded to preserve wires with the keep attribute, but this should be configurable.As a temporary example this includes an
example_dt
pass which recursively traverses a netlist and performs a topological sort of the cells and signals, logging everything.