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drivertools: Utility code for indexing and traversing signal drivers #4328

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@jix jix commented Apr 10, 2024

This is a work in progress version of a new yosys kernel utility to simplify netlist traversal. The motivating use case is the upcoming functional backend but it also should also simplify some common operations/queries that come up repeatedly in various passes.

It adds DriveBit, DriveChunk and DriveSpec types which are similar to SigBit, SigChunk and SigSpec but can also directly represent cell ports, undriven bits and multiple drivers. For indexing an RTLIL module and for querying signal drivers it comes with a DriverMap type which is somewhat similar to a SigMap but is guaranteed to produce signal drivers as returned representatives.

A DriverMap can also optionally preserve connections via intermediate wires (e.g. querying the driver of a cell input port will return a connected intermediate wire, querying the driver of that wire will return the cell output port that's driving the wire). Currently the behavior is hard-coded to preserve wires with the keep attribute, but this should be configurable.

As a temporary example this includes an example_dt pass which recursively traverses a netlist and performs a topological sort of the cells and signals, logging everything.

@jix jix changed the title drivertools: WIP drivertools: Utility code for indexing and traversing signal drivers Apr 10, 2024
jix added 4 commits April 15, 2024 13:55
This adds a generic non-recursive implementation of Tarjan's linear time
SCC algorithm that produces components in topological order. It can be
instantiated to work directly on any graph representation for which the
enumerate_nodes and enumerate_successors interface can be implemented.
When implementing custom log_... functions or custom overloads for the
core log functions like log_signal it is necessary to return `char *`
that are valid long enough.

The log_... functions implemented in log.cc use either `log_id_cache` or
`string_buf` which both are cleared on log_pop.

This commit adds a public `log_str` function which stores its argument
in the `log_id_cache` and returns the stored copy, such that custom
log functions outside of log.cc can also create strings that remain
valid until the next `log_pop`.
This is already supported by `SigSpec` and since both `SigChunk` and
`SigSpec` implement `extract` which is the multi-bit variant of this,
there is no good reason for `SigChunk` to not support
`SigBit operator[](int offset)`.
It adds `DriveBit`, `DriveChunk` and `DriveSpec` types which are similar
to `SigBit`, `SigChunk` and `SigSpec` but can also directly represent
cell ports, undriven bits and multiple drivers. For indexing an RTLIL
module and for querying signal drivers it comes with a `DriverMap` type
which is somewhat similar to a `SigMap` but is guaranteed to produce
signal drivers as returned representatives.

A `DriverMap` can also optionally preserve connections via intermediate
wires (e.g. querying the driver of a cell input port will return a
connected intermediate wire, querying the driver of that wire will
return the cell output port that's driving the wire).
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jix commented Apr 15, 2024

I did some minor cleanup of the commit history and moved the temporary example pass as well as parts of the functional backend that go beyond drivertools into a separate branch at https://github.com/jix/yosys/tree/functional.

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